FPGA design and UVM verification for satellites

Problem

Satellite subsystems demand high-reliability digital design and exhaustive, traceable, reproducible functional verification.

Solution

FPGA IP core design and UVM functional verification of subsystems —power, data, imaging, communications and control— at three levels: RTL, Netlist and Post-Place & Route.

Technology

VHDL / Verilog / SystemVerilog, UVM and a per-protocol agent library (SpaceWire, CCSDS, CAN/SpaceCAN, AMBA, SPI, RS422).

Outcome

Subsystems verified with full traceability and reproducible baselines, plus a reusable verification IP library.

Deliverables

RTL/HDL, UVM testbench, coverage models, PASS/FAIL reports, traceability matrices and bitstream.

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